In BCH-type decoders such as, e.g., Reed-Solomon decoders, slower decoders process one symbol per clock cycle. Parallel processing—processing more than one symbol per clock cycle—greatly improves throughput. Even with a parallelism of ‘2’—i.e., processing two symbols in parallel per clock cycle—improves throughput.
Depending on the type of code and the code parameters, the number of symbols received per codeword may not divide evenly into a number of clock cycles. One solution is to stop processing at a codeword boundary, even if more time remains in the current clock cycle. However, such a solution, in which there periodically is a clock cycle during which the decoder is inactive during a portion of that clock cycle, wastes resources. Another solution is to provide a second decoder, or at least a partial decoder including at least its own syndrome calculation circuitry, that takes over at the codeword boundary. According to this option, both decoders (or partial decoders) operate during respective portions of the overlap clock cycle, but during other clock cycles only one decoder is active while the other decoder (or partial decoder) is idle.
Building and operating a decoder circuit is straightforward when the code parameters—e.g., codeword length, number of parity symbols—and data rate are known in advance. However, decoders frequently need to operate with different parameters even in a fixed circuit such as an application-specific integrated circuit (ASIC). And for a programmable integrated circuit device—e.g., a field-programmable gate array (FPGA)—where the end-user circuit design is unknown, even more flexibility may be necessary, further complicating the situation.